As the operating frequencies of microprocessors go beyond 25 MHz clock speeds, a typical design may obtain the clock signals needed by the processor and its peripherals by multiplying a low speed clock source rather than dividing a high speed clock source. While a clock source having a speed exactly equal to the require clock speed could be used, such an approach is usually not utilized since 1) higher frequently crystals cost more; 2) special oscillator circuits would need to be designed; and 3) external RC components would need to be added to isolate the fundamental frequency from its overtones (harmonics). Although, in general, it is possible to obtain a reliable lower speed clock from a higher speed clock source by dividing a higher speed crystal source, due to the expense of obtaining a high speed clock oscillator circuit, most system designers rely upon a clock source with a lower than required speed clock and multiply that clock to obtain the desired higher clock speed. Additionally, if the input clock source and output clock need to be completely synchronized, the multiplication technique is preferred since techniques used to divide a high speed clock to obtain a lower clock speed usually result in the output clock not being synchronized with the input clock thereby requiring additional circuitry to accomplish synchronization.
To perform the multiplication function on an input clock source, a digital or analog phase locked loop (PLL) or a synchronous delay line (SDL) may be utilized. A suitable SDL for this purpose is described in U.S. Pat. No. 4,980,585. See FIGS. 1A and 1B of the patent which describe a suitable PLL and FIGS. 2-9 of the patent which describe a suitable SDL and supporting elements.